IEEE

IEEE 1838-2019

IEEE Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits

IEEE 1838-2019

IEEE Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits


IEEE 1838-2019

Стандарт IEEE для тестирования архитектуры доступа для трехмерных штабелей интегральных схем


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13.03.2020
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IEEE 1838-2019 IEEE Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits

IEEE 1838-2019 Стандарт IEEE для тестирования архитектуры доступа для трехмерных штабелей интегральных схем

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IEEE Std 1838(TM)-2019 standardizes mandatory and optional on-chip hardware components for 3D test access. It is intended that in the future a standard is developed for a formal, computer-readable language in which implementation choices for the three-dimensional design-for-test (3D-DfT) hardware can be specified and described. An idea of a language/data structure has been described in [B5].The aim of IEEE Std 1838 is to define at die-level standardized and scalable 3D-DfT features based on and working with digital scan-based test access, such that when compliant dies are stacked, a stack-level 3D-DfT test access architecture emerges with a minimum functionality and many optional extensions. IEEE Std 1838 provides a modular test access architecture, in which dies and interconnect layers between adjacent stacked dies can be tested individually. The focus of the standard is testing the intra-die circuitry as well as the inter-die interconnects in pre-bond, mid-bond, and post-bond cases in pre-packaging, post-packaging, and boardlevel situations.The standard provides test access via a mandatory one-bit (‘serial’) input/output test port and optional multi-bit (‘parallel’) test ports. The standard is die-centric, i.e., compliance to the standa

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[2] IEEE Computer Society

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